 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| CD4034BMS December 1992 CMOS 8-Stage Static Bidirectional Parallel/Serial Input/Output Bus Register Description CD4034BMS is a static eight-stage parallel-or serial-input parallel-output register. It can be used to: 1) bidirectionally transfer parallel information between two buses, 2) convert serial data to parallel form and direct the parallel data to either of two buses, 3) store (recirculate) parallel data, or 4) accept parallel data from either of two buses and convert that data to serial form. Inputs that control the operations include a single-phase CLOCK (CL), A DATA ENABLE (AE), ASYNCHRONOUS/SYNCHRONOUS (A/S), A-BUS-TO-B-BUS/B-BUS-TO-A-BUS (A/B), and PARALLEL/SERIAL (P/S). Data inputs include 16 bidirectional parallel data lines of which the eight A data lines are inputs (3-state outputs) and the B data lines are outputs (inputs) depending on the signal level on the A/B input. In addition, an input for SERIAL DATA is also provided. All register stages are D-type master-slave flip-flops with separate master and slave clock inputs generated internally to allow synchronous or asynchronous data transfer from master to slave. Isolation from external noise and the effects of loading is provided by output buffering. Features * High Voltage Types (20V Rating) * Bidirectional Parallel Data Input * Parallel or Serial Inputs/Parallel Outputs * Asynchronous or Synchronous Parallel Data Loading * Parallel Data-Input Enable on "A" Data Lines (3-State Output) * Data Recirculation for Register Expansion * Multipackage Register Expansion * Fully Static Operation DC-to-10MHz (typ.) at VDD = 10V * Standardized Symmetrical Output Characteristics * 100% Tested for Quiescent Current at 20V * 5V, 10V and 15V Parametric Ratings * Maximum Input Current of 1A at 18V Over Full Package-Temperature Range; - 100nA at 18V and +25oC * Noise Margin (Over Full Package Temperature Range): - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V * Meets All Requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of `B' Series CMOS Devices" Pinout CD4034BMS TOP VIEW 81 24 VDD 23 8 22 7 21 6 20 5 19 4 18 3 17 2 16 1 15 CLOCK 14 A/S 13 P/S "A" DATA LINES Applications "B" DATA LINES 72 63 54 45 36 27 18 "A" ENABLE 9 SERIAL INPUT 10 A/B 11 VSS 12 * Parallel Input/Parallel Output, Serial Input/Parallel Output, Serial Input/Serial Output Register * Shift Right/Shift Left Register * Shift Right/Shift Left With Parallel Loading * Address Register * Buffer Register * Bus System Register with Enable Parallel Lines at Bus Side * Double Bus Register System * Up-Down Johnson or Ring Counter * Pseudo-Random Code Generators * Sample and Hold Register (Storage, Counting, Display) * Frequency and Phase Comparator CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright (c) Intersil Corporation 1999 File Number 3307 7-837 CD4034BMS Parallel Operation A high P/S input signal allows data transfer into the register via the parallel data lines synchronously with the positive transition of the clock provided the A/S input is low. If the A/S input is high the transfer is independent of the clock. The direction of data flow is controlled by the A/B input. When this signal is high the A data lines are inputs (and B data lines are outputs); a low A/B signal reverses the direction of data flow. The AE input is an additional feature which allows many registers to feed data to a common bus. The A DATA lines are enabled only when this signal is high. Data storage through recirculation of data in each register stage is accomplished by making the A/B signal high and the AE signal low. A DATA LINES Functional Diagram SI AE A/B A/S P/S CL SI Q STEERING LOGIC A1 B1 SI Serial Operation A low P/S signal allows serial data to transfer into the register synchronously with the positive transition of the clock. The A/S input is internally disabled when the register is in the serial mode (asynchronous serial operation is not allowed). The serial data appears as output data on either the B lines (when A/B is high) or the A lines (when A/B is low and the AE signal is high). Register expansion can be accomplished by simply cascading CD4034BMS packages. The CD4034BMS is supplied in these 24 lead outline packages: Braze Seal DIP Ceramic Flatpack H4V H4P Q A8 SI B8 7-838 B DATA LINES 6 STAGES Specifications CD4034BMS Absolute Maximum Ratings DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 1/32 Inch (1.59mm 0.79mm) from case for 10s Maximum Reliability Information Thermal Resistance . . . . . . . . . . . . . . . . ja jc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W o Maximum Package Power Dissipation (PD) at +125 C For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS 1 2 VDD = 18V, VIN = VDD or GND Input Leakage Current Except A and B Lines IIL VIN = VDD or GND VDD = 20 VDD = 18V Input Leakage Current Except A and B Lines IIH VIN = VDD or GND VDD = 20 VDD = 18V Output Voltage Output Voltage Output Current (Sink) Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) Output Current (Source) N Threshold Voltage P Threshold Voltage Functional VOL15 VOH15 IOL5 IOL10 IOL15 IOH5A IOH5B IOH10 IOH15 VNTH VPTH F VDD = 15V, No Load VDD = 15V, No Load (Note 3) VDD = 5V, VOUT = 0.4V VDD = 10V, VOUT = 0.5V VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V VDD = 5V, VOUT = 2.5V VDD = 10V, VOUT = 9.5V VDD = 15V, VOUT = 13.5V VDD = 10V, ISS = -10A VSS = 0V, IDD = 10A VDD = 2.8V, VIN = VDD or GND VDD = 20V, VIN = VDD or GND VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Input Voltage Low (Note 2) Input Voltage High (Note 2) Input Voltage Low (Note 2) Input Voltage High (Note 2) Tri-State Output Leakage VIL VIH VIL VIH IOZL VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V VIN = VDD or GND VOUT = 0V VDD = 20V VDD = 18V Tri-State Output Leakage IOZH VIN = VDD or GND VOUT = VDD VDD = 20V VDD = 18V NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs. 3 1 2 3 1 2 3 1, 2, 3 1, 2, 3 1 1 1 1 1 1 1 1 1 7 7 8A 8B 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1 2 3 1 2 3 +25oC, LIMITS TEMPERATURE +25oC +125 C -55oC +25oC +125oC -55oC +25oC +125oC -55oC +125oC, +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +125oC -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC +125oC -55oC +25oC +125oC -55oC 3.5 11 -0.4 -12 -0.4 1.5 4 0.4 12 0.4 V V V V A A A A A A -55oC o PARAMETER Supply Current SYMBOL IDD CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND MIN -100 -1000 -100 0.53 1.4 3.5 -2.8 0.7 MAX 10 1000 10 100 1000 100 50 -0.53 -1.8 -1.4 -3.5 -0.7 2.8 UNITS A A A nA nA nA nA nA nA mV V mA mA mA mA mA mA mA V V V +25oC, +125oC, -55oC 14.95 VOH > VOL < VDD/2 VDD/2 3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max. 7-839 Specifications CD4034BMS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS TEMPERATURE 9 10, 11 9 10, 11 9 10, 11 9 10, 11 9 10, 11 +25oC +125oC, -55oC LIMITS MIN o PARAMETER Propagation Delay Parallel In to Parallel Out Propagation Delay 3 State AE to Out `A' Propagation Delay 3-State AE to Out `A' Transition Time SYMBOL TPHL TPLH TPLZ TPHZ TPZL TPZH TTHL TTLH FCL CONDITIONS VDD = 5V, VIN = VDD or GND (Notes 1, 2) VDD = 5V, VIN = VDD or GND (Notes 2, 3) VDD = 5V, VIN = VDD or GND (Notes 2, 3) VDD = 5V, VIN = VDD or GND (Notes 1, 2) VDD = 5V, VIN = VDD or GND (Note 2) MAX 700 945 400 540 400 540 200 270 - UNITS ns ns ns ns ns ns ns ns MHz MHz +25oC +125oC, -55oC +25oC +125oC, -55oC +25 C +125 C, -55 C +25 C +125oC, -55oC o o o 2 1.48 Maximum Clock Input Frequency NOTES: 1. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. 3. CL = 50pF, RL = 1K, Input TR, TF < 20ns. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS VDD = 5V, VIN = VDD or GND NOTES 1, 2 TEMPERATURE -55oC, +25oC +125oC VDD = 10V, VIN = VDD or GND 1, 2 -55oC, +25oC +125oC VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC +125oC Output Voltage Output Voltage Output Voltage Output Voltage Output Current (Sink) VOL VOL VOH VOH IOL5 VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, VOUT = 0.4V 1, 2 1, 2 1, 2 1, 2 1, 2 +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +125oC -55oC Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1, 2 +125oC -55oC Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, 2 +125oC -55oC Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1, 2 +125oC -55oC Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1, 2 +125oC -55oC Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1, 2 +125oC -55oC 4.95 9.95 0.36 0.64 0.9 1.6 2.4 4.2 50 -0.36 -0.64 -1.15 -2.0 -0.9 -1.6 mV V V mA mA mA mA mA mA mA mA mA mA mA mA MIN MAX 5 150 10 300 10 600 50 UNITS A A A A A A mV 7-840 Specifications CD4034BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Output Current (Source) SYMBOL IOH15 CONDITIONS VDD =15V, VOUT = 13.5V NOTES 1, 2 TEMPERATURE +125oC -55 C Input Voltage Low Input Voltage High Propagation Delay Parallel In to Parallel Out Propagation Delay Serial to Parallel Out VIL VIH TPHL TPLH TPHL TPLH VDD = 10V, VOH > 9V, VOL < 1V VDD = 10V, VOH > 9V, VOL < 1V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V Propagation Delay 3-State AE to Out `A' Propagation Delay 3-State AE to Out `A' Transition Time TPLZ TPHZ TPZL TPZH TTLH TTHL FCL VDD = 10V VDD = 15V VDD = 10V VDD = 15V VDD = 10V VDD = 15V VDD = 10V VDD = 15V TS VDD = 5V VDD = 10V VDD = 15V Minimum Data Setup Time Parallel Data to Clock Minimum Clock Pulse Width TS VDD = 5V VDD = 10V VDD = 15V TW VDD = 5V VDD = 10V VDD = 15V Maximum Clock Rise and Fall Time (Note 5) TRCL TFCL VDD = 5V VDD = 10V VDD = 15V Minimum High Level Pulse Width AE, P/S, A/S TW VDD = 5V VDD = 10V VDD = 15V Input Capacitance NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. CL = 50pF, RL = 1K, Input TR, TF < 20ns. 5. If more than one unit is cascaded, tRCL should be made less than or equal to the sum of the transition time and the fixed propagation delay of the output of the driving stage for the estimated capacitive load. CIN Any Input 1, 2 1, 2 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3, 4 1, 2, 3, 4 1, 2, 3, 4 1, 2, 3, 4 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2 +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC +25oC +25 C +25 C +25oC +25oC +25oC +25oC +25 C +25oC +25oC +25 oC o o o o MIN +7 700 5 7 - MAX -2.4 -4.2 3 240 170 240 170 160 120 160 120 100 80 160 60 40 50 30 20 250 100 70 15 15 15 350 140 80 7.5 UNITS mA mA V V ns ns ns ns ns ns ns ns ns ns ns MHz MHz ns ns ns ns ns ns ns ns ns s s s ns ns ns pF Maximum Clock Input Frequency Minimum Data Setup Time Serial Data to Clock +25oC +25 C +25 oC o +25oC +25 oC +25oC +25oC +25 oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC 7-841 Specifications CD4034BMS TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current N Threshold Voltage N Threshold Voltage Delta P Threshold Voltage P Threshold Voltage Delta Functional SYMBOL IDD VNTH VTN VTP VTP F CONDITIONS VDD = 20V, VIN = VDD or GND VDD = 10V, ISS = -10A VDD = 10V, ISS = -10A VSS = 0V, IDD = 10A VSS = 0V, IDD = 10A VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Propagation Delay Time TPHL TPLH VDD = 5V 1, 2, 3, 4 +25oC NOTES 1, 4 1, 4 1, 4 1, 4 1, 4 1 TEMPERATURE +25oC +25oC +25oC +25oC +25oC +25oC MIN -2.8 0.2 VOH > VDD/2 MAX 25 -0.2 1 2.8 1 VOL < VDD/2 1.35 x +25oC Limit UNITS A V V V V V ns NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 3. See Table 2 for +25oC limit. 4. Read and Record TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC PARAMETER Supply Current - MSI-2 Output Current (Sink) Output Current (Source) SYMBOL IDD IOL5 IOH5A 1.0A 20% x Pre-Test Reading 20% x Pre-Test Reading DELTA LIMIT TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUP Initial Test (Pre Burn-In) Interim Test 1 (Post Burn-In) Interim Test 2 (Post Burn-In) PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) Final Test Group A Group B Subgroup B-5 Subgroup B-6 Group D MIL-STD-883 METHOD 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 Sample 5005 Sample 5005 Sample 5005 Sample 5005 GROUP A SUBGROUPS 1, 7, 9 1, 7, 9 1, 7, 9 1, 7, 9, Deltas 1, 7, 9 1, 7, 9, Deltas 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas 1, 7, 9 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2, 3 Subgroups 1, 2, 3, 9, 10, 11 IDD, IOL5, IOH5A READ AND RECORD IDD, IOL5, IOH5A IDD, IOL5, IOH5A IDD, IOL5, IOH5A NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. TABLE 7. TOTAL DOSE IRRADIATION MIL-STD-883 METHOD 5005 TEST PRE-IRRAD 1, 7, 9 POST-IRRAD Table 4 READ AND RECORD PRE-IRRAD 1, 9 POST-IRRAD Table 4 CONFORMANCE GROUPS Group E Subgroup 2 7-842 Specifications CD4034BMS TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION Static Burn-In 1 Note 1 Static Burn-In 2 Note 1 Dynamic Burn-In Note 1 Irradiation Note 2 NOTE: 1. Each pin except VDD and GND will have a series resistor of 10K 5%, VDD = 18V 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V 0.5V OPEN 1-8 1-8 1-8 GROUND 12, 15 - 23 12 1 - 8, 11 - 14 12 VDD 9 - 11, 13, 14, 24 9 - 11, 13 - 24 9, 24 9 - 11, 13 - 24 16 - 23 15 10 9V -0.5V 50kHz 25kHz Logic Diagram * AB N M M M N L * AE K K P/S L VDD * P/S P/S CLS * A/S CLS VSS CLM *INPUTS PROTECTED BY CMOS PROTECTION NETWORK * CLOCK CLM FLIP-FLOP TRUTH TABLE INPUTS CLM CLS D 0 0 0 X 1 1 1 1 = High Level 0 = Low Level OUTPUT Q 0 0 Invalid Condition 0 1 1 Invalid Condition X = Don't Care 7-843 CD4034BMS trCL CLOCK INPUT "A" OR "B" DATA INPUTS tTLH tTHL tfCL VDD 90% 50% 10% 0 INPUT ** tSLH ** tSHL 50% 0 tTLH tTHL VDD 90% 50% 10% 0 "B" OR "A" DATA OUTPUTS VDD 90% 50% 10% 0 OUTPUT tPLH SERIAL INPUT, A/B, P/S, or A/S inputs tPHL tPLH tPHL *Input refers to any of the "A" or "B" data inputs, "A" ENABLE, **tSLH and tSHL are Set-Up times FIGURE 1. ASYNCHRONOUS OPERATION PROPAGATION DELAY TIME AND TRANSITION TIME FIGURE 2. SYNCHRONOUS OPERATION PROPAGATION DELAY TIMES, TRANSITION TIMES, AND SET-UP TIMES CLOCK A ENABLE P/S A/B A/S SERIAL DATA A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 B DATA LINES ARE OUTPUTS A DATA LINES ARE OUTPUTS FIGURE 3. TIMING DIAGRAM 7-844 CD4034BMS Typical Performance Characteristics AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25oC OUTPUT LOW (SINK) CURRENT (IOL) (mA) OUTPUT LOW (SINK) CURRENT (IOL) (mA) 30 25 20 15 10 5 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 15.0 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 10.0 7.5 5.0 2.5 10V 10V 5V 0 5 10 15 5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 4. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V FIGURE 5. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V -5 0 0 -5 -10 -15 0 0 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) 105 -10V -20 -25 -10V -10 -15V -30 -15V -15 FIGURE 6. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS FIGURE 7. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS 106 8 6 4 2 AMBIENT TEMPERATURE (TA TRANSITION TIME (tTHL, tTLH) (ns) ) = +25oC POWER DISSIPATION PER GATE (PD) (W) AMBIENT TEMPERATURE (TA) = +25oC SUPPLY VOLTAGE (VDD) = 15V 105 8 6 4 200 SUPPLY VOLTAGE (VDD) = 5V 150 104 2 8 6 4 2 10V 10V 5V 100 10V 50 15V 103 8 6 4 2 CL = 50pF CL = 15pF 2 4 68 2 4 68 2 4 68 2 4 68 2 4 68 0 0 102 20 40 60 80 100 LOAD CAPACITANCE (CL) (pF) 1 103 10 102 INPUT FREQUENCY (fI) (kHz) 104 FIGURE 8. TYPICAL TRANSITION TIME AS A FUNCTION OF LOAD CAPACITANCE FIGURE 9. TYPICAL DYNAMIC POWER DISSIPATION AS A FUNCTION OF CLOCK FREQUENCY 7-845 CD4034BMS Typical Performance Characteristics [A(B) PAR DATA IN B(A) PAR DATA OUT] PROPAGATION DELAY TIME (tPHL, tPLH) (ns) (Continued) AMBIENT TEMPERATURE (TA) = +25oC 700 600 500 400 300 200 100 15V 0 20 50 60 70 80 90 30 40 LOAD CAPACITANCE (CL) (pF) 100 10V SUPPLY VOLTAGE (VDD) = 5V FIGURE 10. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE [A(B) PARALLEL DATA INPUT TO B(A) PARALLEL DATA OUTPUT, SYNCHRONOUS OR ASYNCHRONOUS]) 7-846 CD4034BMS 1 OF 8 STAGES K An p n M VSS PROTECTION NETWORK ON ALL "A" AND "B" DATA INPUTS SERIAL DATA D K Q' Q' VDD P/S p n P/S CLM p n CLM CLM p n CLM CLS p n CLS CLS p n Q' L p CLS N VSS N VDD M VSS VDD VSS PROTECTION NETWORK ON SERIAL DATA INPUT n Q (TO NEXT STAGE D) L Bn FIGURE 11. REGISTER STAGE LOGIC DIAGRAM (1 OF 8 STAGES) TRUTH TABLE REGISTER INPUT-LEVELS AND RESULTING REGISTER OPERATION "A" ENABLE 0 0 0 0 0 P/S 0 0 1 1 1 A/B 0 1 0 0 1 A/S X X 0 1 0 OPERATION* Serial Mode; Synch. Serial Data Input, "A" Parallel Data Outputs Disabled Serial Mode; Synch. Serial Data Input, "B" Parallel Data Output Parallel Mode; "B" Synch. Parallel Data Inputs, "A" Parallel Data Outputs Disabled Parallel Mode; "B" Asynch. Parallel Data Inputs, "A" Parallel Data Outputs Disabled Parallel Mode; "A" Parallel Data Inputs Disabled, "B" Parallel Data Outputs, Synch. Data Recirculation Parallel Mode; "A" Parallel Data Inputs Disabled, "B" Parallel Data Outputs, Asynch. Data Recirculation Serial Mode; Synch. Serial Data Input, "A" Parallel Data Output Serial Mode; Synch. Serial Data Input, "B" Parallel Data Output Parallel Mode; "B" Synch. Parallel Data Input, "A" Parallel Data Output Parallel Mode; "B" Asynch. Parallel Data Input, "A" Parallel Data Output Parallel Mode; "A" Synch, Parallel Data Input, "B" Parallel Data Output Parallel Mode; "A" Asynch. Parallel Data Input, "B" Parallel Data Output 0 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 0 1 0 0 1 1 X X 0 1 0 1 *Outputs change at positive transition of clock in the serial mode and when the A/S control input is "low" in the parallel mode. During transfer from parallel to serial operation A/S should remain low in order to prevent DS transfer into Flip Flops. 1 = High Level 0 = Low Level X = Don't Care 7-847 CD4034BMS Applications VDD VDD SERIAL DATA VDD AE A PARALLEL SI DATA A/B CD4034 A/S CL B PARALLEL DATA P/S SERIAL DATA VDD AE A PARALLEL SI DATA A/B CD4034 A/S CL B PARALLEL DATA P/S SERIAL DATA P/S A/S CL FIGURE 12. 16-BIT PARALLEL IN/PARALLEL OUT, PARALLEL IN/SERIAL OUT, SERIAL IN/PARALLEL OUT SERIAL IN/SERIAL OUT REGISTER "A" ENABLE SERIAL DATA AE A PARALLEL SI DATA A/B CD4034 A/S CL B PARALLEL DATA P/S SERIAL DATA AE A PARALLEL SI DATA A/B CD4034 A/S CL B PARALLEL DATA P/S SERIAL DATA A/B CL FIGURE 13. 16-BIT SERIAL IN/GATED PARALLEL OUT REGISTER BUS LINES (SINGLE) DOUBLE - BUS SYSTEM (ENABLE INPUTS ON BOTH SIDES) MEMORY UNIT P/S AE 1 1 CD4034 2 2 3 W REG 3 4 4 B A 5 5 6 6 7 7 8 8 SI A/B A/S CL AE P/S 1 1 2 2 X(1) 3 3 REG 4 4 A B 5 5 CD4034 6 6 7 7 8 8 SI A/B A/S CL P/S AE 1 1 2 2 X(2) 3 3 REG 4 4 B A 5 5 CD4034 6 6 7 7 8 8 SI A/B A/S CL TO 2ND BUS SYSTEM PERIPHERAL UNIT SI A/B A/S CL P/S AE 1 1 2 2 3 Y REG 3 4 4 B A 5 5 CD4034 6 6 7 7 8 8 SI A/B A/S CL P/S AE 1 1 2 2 3 Z REG 3 4 4 B A 5 5 6 CD4034 6 7 7 8 8 ARITHMETIC UNIT THE "A" ENABLE (AE) AND A/B SIGNALS CONTROL ALL COMBINATIONS OF TRANSFER BETWEEN THE REGISTERS AND BUS SYSTEMS FIGURE 14. SINGLE AND DOUBLE-BUS SYSTEMS 7-848 CD4034BMS Applications (Continued) SHIFT LEFT OUTPUT "A" ENABLE AE SHIFT LEFT/ SHIFT RIGHT P/S "A" PARALLEL DATA "A" PARALLEL DATA SHIFT RIGHT OUTPUT AE 1 SI P/S A/S CL A/B 1 8 AE 1 SI P/S A/S CL A/B 1 8 REG. 2 CD4034 SHIFT RIGHT INPUT REG. 1 CD4034 CLOCK A/S PARALLEL ENTRY SHIFT LEFT INPUT* A/S CL AE AE 1 SI P/S VDD A/S CL A/B 1 A PARALLEL DATA REG. 3 CD4034 8 AE 1 SI P/S VDD A/S CL A/B 1 A PARALLEL DATA REG. 4 CD4034 B PARALLEL DATA 8 B PARALLEL DATA 8 8 FIGURE 15. SHIFT RIGHT/SHIFT LEFT WITH PARALLEL INPUTS A "High" ("Low") on the shift Left/Shift Right input allows serial data on the Shift Left Input (Shift Right Input) to enter the register on the positive transition of the clock signal. A "high" on the "A" Enable Input disables the "A" parallel data lines Reg. 1 and 2 and enables the "A" data lines on registers 3 and 4 and allows parallel data into registers 1 and 2. Other logic schemes may be used in place of registers 3 and 4 for parallel loading. When parallel inputs are not used Reg. 3 and 4 and associated logic are not required. * Shift left input must be disabled during parallel entry. SAMPLE/HOLD AE SERIAL DATA VDD CLOCK SI A/B A/S CL P/S A PARALLEL DATA CD4034 B PARALLEL DATA CD4016 P/S N=1-8 SERIAL OUTPUT N STAGE SELECTION TO DISPLAY ETC SERIAL DATA VDD A/S CLOCK AE SI A/B A/S CL P/S 1 1 "A" PARALLEL DATA CD4034 "B" PARALLEL DATA 8 8 CD4016 FIGURE 16. N-STAGE SHIFT REGISTER WITH FIXED SERIAL OUTPUT LINE FIGURE 17. SAMPLE AND HOLD REGISTER - SERIAL/PARALLEL IN - PARALLEL OUT 7-849 CD4034BMS Chip Dimensions and Pad Layout Dimension in parenthesis are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch). METALLIZATION: PASSIVATION: Thickness: 11kA - 14kA, AL. 10.4kA - 15.6kA, Silane BOND PADS: 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 850 |
Price & Availability of CD4034BMS
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |